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19-1236; Rev 0; 6/97
KIT ATION EVALU BLE AVAILA
Low-Power, 90Msps, Dual 6-Bit ADC
____________________________Features
o Two Matched 6-Bit ADCs o High Sampling Rate: 90Msps per ADC o Low Power Dissipation: 350mW o Excellent Dynamic Performance: 5.85 ENOB with 20MHz Analog Input 5.7 ENOB with 50MHz Analog Input o 1/4LSB INL and DNL (typ) o Internal Bandgap Voltage Reference o Internal Oscillator with Overdrive Capability o 55MHz (-0.5dB) Bandwidth Input Amplifiers with True Differential Inputs o User-Selectable Input Full-Scale Range (125mVp-p, 250mVp-p, or 500mVp-p) o 1/4LSB Channel-to-Channel Offset Matching (typ) o 0.1dB Gain and 0.5 Phase Matching (typ) o Single-Ended or Differential Input Drive o Flexible, 3.3V, CMOS-Compatible Digital Outputs
_______________General Description
The MAX1003 is a dual, 6-bit analog-to-digital converter (ADC) that combines high-speed, low-power operation with a user-selectable input range, an internal reference, and a clock oscillator. The dual parallel ADCs are designed to convert in-phase (I) and quadrature (Q) analog signals into two 6-bit, offset-binary-coded digital outputs at sampling rates up to 90Msps. The ability to directly interface with baseband I and Q signals makes the MAX1003 ideal for use in direct-broadcast satellite, VSAT, and QAM16 demodulation applications. The MAX1003 input amplifiers feature true differential inputs, a -0.5dB analog bandwidth of 55MHz, and userprogrammable input full-scale ranges of 125mVp-p, 250mVp-p, or 500mVp-p. With an AC-coupled input signal, matching performance between input channels is typically better than 0.1dB gain, 1/4LSB offset, and 0.5 phase. Dynamic performance is 5.85 effective number of bits (ENOB) with a 20MHz analog input signal, or 5.7 ENOB with a 50MHz signal. The MAX1003 operates with +5V analog and +3.3V digital supplies for easy interfacing to +3.3V-logic-compatible digital signal processors and microprocessors. It comes in a 36-pin SSOP package.
MAX1003
________________________Applications
Direct Broadcast Satellite (DBS) Receivers VSAT Receivers Wide Local Area Networks (WLANs) Cable Television Set-Top Boxes
______________Ordering Information
PART MAX1003CAX TEMP. RANGE 0C to +70C PIN-PACKAGE 36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
IOCC+ IIN+ INPUT AMP I
OFFSET CORRECTION I
IOCC6 6
IIN-
ADC I VREF
DATA BUFFER I
DI0-DI5
CLOCK OUT BANDGAP REFERENCE CLOCK DRIVER
DCLK TNK+ TNK-
GAIN
OFFSET CORRECTION Q
QIN+ INPUT AMP Q QOCC+
MAX1003
VREF ADC Q 6 DATA BUFFER Q 6 DQ0-DQ5
QIN-
QOCC-
________________________________________________________________ Maxim Integrated Products
1
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Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
ABSOLUTE MAXIMUM RATINGS
VCC to GND ............................................................-0.3V to 6.5V VCCO to OGND ........................................................-0.3V to 6.5V GND to OGND ........................................................-0.3V to 0.3V Digital and Clock Output Pins to OGND...-0.3V to VCCO (10sec) All Other Pins to GND...............................................-0.3V to VCC Continuous Power Dissipation (TA = +70C) SSOP (derate 11.8mW/C above +70C) ...................941mW Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, <10sec)...........................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V 5%, VCCO = 3.3V 300mV, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity Full-Scale Input Range RES INL DNL VFSH VFSM VFSL Input Open-Circuit Voltage Input Resistance Input Capacitance Common-Mode Voltage Range OSCILLATOR INPUTS Oscillator Input Resistance Digital Outputs Logic-High Voltage Digital Outputs Logic-Low Voltage POWER SUPPLY Supply Current Power-Supply Rejection Ratio Digital Outputs Supply Current Power Dissipation ICC PSRR ICCO PD VCC = 4.75V to 5.25V (Note 3) 20MHz, full-scale I and Q analog inputs, CL = 15pF (Note 4) 350 63 -75 104 -40 21 mA dB mA mW ROSC Other oscillator input tied to VCC + 0.3V 4.8 8 12.1 k DIGITAL OUTPUTS (DI0-DI5, DQ0-DQ5) VOH VOL ISOURCE = 50A ISINK = 400A 0.7VCCO 0.5 V V VAOC RIN CIN VCM Guaranteed by design Other analog input driven with external source (Note 2) 1.75 No missing codes over temperature GAIN = VCC (high gain) GAIN = open (mid gain) GAIN = GND (low gain) 6 -0.5 -0.5 118.75 237.5 475 2.25 13 0.25 0.25 125 250 500 2.35 20 3 0.5 0.5 131.25 262.5 525 2.45 29 5 2.75 V k pF V mVp-p Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
INVERTING AND NONINVERTING ANALOG INPUTS
2
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Low-Power, 90Msps, Dual 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V 5%, VCCO = 3.3V 300mV, TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1003
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below full scale, unless otherwise noted.) Maximum Sample Rate Analog Input -0.5dB Bandwidth fMAX BW ENOBM Effective Number of Bits ENOBH ENOBL Signal-to-Noise plus Distortion Ratio Input Offset (Note 5) Crosstalk Between ADCs Offset Mismatch Between ADCs Amplitude Match Between ADCs Phase Match Between ADCs Clock to Data Propagation Delay Data Valid Skew Input to DCLK Delay Aperture Delay Pipeline Delay SINAD OFF XTLK OMM AM PM (Note 5) -0.5 -0.2 -2 GAIN = GND, open, VCC GAIN = open (mid gain) GAIN = open (mid gain), fIN = 50MHz, -1dB below full scale GAIN = VCC (high gain) GAIN = GND (low gain) GAIN = open (mid gain) I channel Q channel 35.5 -0.5 -0.5 -55 0.25 0.1 0.5 0.5 0.2 2 5.6 90 55 5.85 5.7 5.8 5.85 37 0.5 0.5 dB LSB dB LSB dB degrees Bits Msps MHz
TIMING CHARACTERISTICS (Data outputs: RL = 1M, CL = 15pF) tPD tSKEW tDCLK tAD PD (Note 6) (Note 6) TNK+ to DCLK (Note 6) Figure 8 Figure 8 3.6 1.5 5.3 7.5 1 ns ns ns ns clock cycle
Note 1: Best-fit straight-line linearity method. Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V). However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this commonmode input range (Figures 4 and 5). Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCC supply voltage, expressed in decibels. Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply transients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the digital outputs to a minimum. Note 5: Offset-correction compensation enabled, 0.22F at Q and I compensation inputs (Figures 2 and 3). Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capacitive load on the outputs is 15pF.
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Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
__________________________________________Typical Operating Characteristics
(VCC = +5V 5%, VCCO = 3.3V 300mV, fCLK = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, TA = +25C, unless otherwise noted.)
EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY
MAX1003-01
ANALOG INPUT BANDWIDTH
0 -0.2 MAGNITUDE (dB)
MAX1003-02
EFFECTIVE NUMBER OF BITS vs. SAMPLING/CLOCK FREQUENCY
MAX1003-03
6.0
6.0
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
5.8
5.9
5.6
5.8
-0.4 -0.6 -0.8
5.4
5.7
5.2 fCLK = 90Msps 5.0 10 ANALOG INPUT FREQUENCY (MHz) 100
5.6 fIN = 20MHz
-1.0 1 10 ANALOG INPUT FREQUENCY (MHz) 100
5.5 1 10 CLOCK FREQUENCY (MHz) 100
OSCILLATOR OPEN-LOOP PHASE NOISE vs. FREQUENCY OFFSET
MAX1003-04
FFT PLOT
fIN = 19.9512MHz fCLK = 90.000MHz 1024 POINTS AC COUPLED SINGLE ENDED AVERAGED
MAX1003-05
-50
0
-70 PHASE NOISE (dBc) AMPLITUDE (dB) 1k 10k 100k 1M -20
-90
-110
-40
-130 -60 0 9 18 27 36 45 FREQUENCY OFFSET FROM CARRIER (Hz) FREQUENCY (MHz)
INTEGRAL NONLINEARITY vs. CODE
MAX1003-06
DIFFERENTIAL NONLINEARITY vs. CODE
MAX1003-07
0.50
0.50
0.25 DNL (LSB) INL (LSB)
0.25
0
0
-0.25
-0.25
-0.50 0 10 20 30 CODE 40 50 60 64
-0.50 0 10 20 30 CODE 40 50 60 64
4
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Low-Power, 90Msps, Dual 6-Bit ADC
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7, 11, 12, 18, 19 8 9 10 13 14 15 16 17 20-25 26, 28 27 29 30-35 36 NAME GAIN IOCC+ IOCCIIN+ IINVCC GND VCC TNK+ TNKVCC QINQIN+ QOCCQOCC+ DQ5-DQ0 VCCO OGND DCLK DI0-DI5 VCC FUNCTION Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1). Positive I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground for DC-coupled inputs. Negative I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground for DC-coupled inputs. I-Channel Noninverting Analog Input I-Channel Inverting Analog Input +5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 7). Analog Ground +5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 11). Positive Oscillator/Clock Input Negative Oscillator/Clock Input +5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 12). Q-Channel Inverting Analog Input Q-Channel Noninverting Analog Input Negative Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground for DC-coupled inputs. Positive Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled inputs. Ground for DC-coupled inputs. Q-Channel Digital Outputs 0-5. DQ5 is the most significant bit (MSB). Digital Output Supply, +3.3V 300mV. Bypass each with a 47pF capacitor to OGND (pin 27). Digital Output Ground Digital Clock Output. Frames the output data. I-Channel Digital Outputs 0-5. DI5 is the most significant bit (MSB). +5V 5% Supply. Bypass with a 0.01F capacitor to GND (pin 19).
MAX1003
_______________Detailed Description
Converter Operation
The MAX1003 contains two 6-bit analog-to-digital converters (ADCs), a buffered voltage reference, and oscillator circuitry. The ADCs use a flash conversion technique to convert an analog input signal into a 6-bit parallel digital output code. The MAX1003's unique design includes 63 fully differential comparators and a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. The control logic interfaces easily to most digital signal processors (DSPs) and microprocessors (Ps) with +3.3V CMOScompatible logic interfaces. Figure 1 shows the MAX1003 in a typical application.
Programmable Input Amplifiers
The MAX1003 has two (I and Q) programmable-gain input amplifiers with a -0.5dB bandwidth of 55MHz and true differential inputs. To maximize performance in high-speed systems, each amplifier has less than 5pF of input capacitance. The input amplifier gain is programmed, via the GAIN pin, to provide three possible input full-scale ranges (FSRs) as shown in Table 1.
Table 1. Input Amplifier Programming
GAIN GND Open VCC INPUT FULL-SCALE RANGE (mVp-p) 500 250 125 5
_______________________________________________________________________________________
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
Single-ended and differential AC-coupled input circuits are shown in Figures 2 and 3. Each of the amplifier inputs is internally biased to a 2.35V reference through a 20k resistor, eliminating external DC bias circuits. A series 0.1F capacitor is required at each amplifier input for AC-coupled signals. When operating with AC-coupled inputs, the input amplifiers' DC offset voltage is nulled to within 1/2LSB by an on-chip offset-correction amplifier. An external compensation capacitor is required to set the dominant pole of the offset-correction amplifier's frequency response (Figures 2 and 3). The compensation capacitor will determine the low-frequency corner of the analog input response according to the following formula: fc = 1 / (0.1 x C) where C is the value of the compensation capacitor in F, and fc is the corner frequency in Hz.
LNB 75 CABLE 950MHz TO 2150MHz F-CONNECTOR INPUT
KU BAND
OR VARACTOR-TUNED PRESELECTION FILTER FROM TANK VOLTAGE AGC RFIN 6 BITS RFIN 0 90 IOUT DATA BUFFER IIN VCC AGC
90Msps
CLK IN
MAX2102
6 BITS DATA BUFFER QIN
DSP
QOUT
EXTERNAL VCO
LO DIV LO ADC CLOCK
TANK OR TSA5055 or EQUIV. MOD GND TANK
MAX1003
MODCTL
SYNTHESIZER FIN CAR
Figure 1. Commercial Satellite Receiver System
6 _______________________________________________________________________________________
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
0.22F 0.22F
_OCC+
_OCCOFFSET CORRECTION
_OCC+
_OCCOFFSET CORRECTION
0.1F
_IN+ INPUT AMP _IN0.1F 20k 20k
0.1F
_IN+ INPUT AMP _IN-
VSOURCE
VSOURCE
0.1F
MAX1003
2.35V INTERNAL REFERENCE
20k
20k
MAX1003
2.35V INTERNAL REFERENCE
Figure 2. Single-Ended AC-Coupled Input
OFFSET CORRECTION DISABLED
Figure 3. Differential AC-Coupled Input
OFFSET CORRECTION DISABLED
_OCC+
_OCCOFFSET CORRECTION
_OCC+
_OCCOFFSET CORRECTION
_IN+ VSOURCE _IN20k VREF 1.75V TO 2.75V 20k INPUT AMP VSOURCE
_IN+ INPUT AMP _IN-
MAX1003
2.35V INTERNAL REFERENCE DIFFERENTIAL SOURCE WITH COMMON MODE FROM 1.75V TO 2.75V.
20k
20k
MAX1003
2.35V INTERNAL REFERENCE
Figure 4. Single-Ended DC-Coupled Input
Figure 5. Differential DC-Coupled Input
For applications where a DC component of the input signal is present, Figures 4 and 5 show single-ended and differential DC-coupled input circuits. The amplifiers' input common-mode voltage range extends from 1.75V to 2.75V. To prevent attenuation of the input signal's DC component in this mode, disable the offsetcorrection amplifier by grounding the _OCC+ and _OCC- pins for the I and Q blocks (Figures 4 and 5).
ADCs
The I and Q ADC blocks receive the analog signals from the respective I and Q input amplifiers. The ADCs use flash conversion with 63 fully differential comparators to digitize the analog input signal into a 6-bit output in offset binary format.
_______________________________________________________________________________________
7
Low-Power, 90Msps, Dual 6-Bit ADC
The MAX1003 features a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. Dynamic encoding errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for typical converters can be incorrect, including false full- or zero-scale outputs. The MAX1003's unique design reduces the magnitude of this type of error to 1LSB.
MAX1003
Oscillator Circuit
The MAX1003 includes a differential oscillator, which is controlled by an external parallel resonant (tank) network as shown in Figure 6. Alternatively, the oscillator may be overdriven with an external clock source as shown in Figure 7.
Internal Voltage Reference
An internal buffered bandgap reference is included on the MAX1003 to drive the ADCs' reference ladders. The on-chip reference and buffer eliminate any external (high-impedance) connections to the reference ladder, minimizing the potential for noise coupling from external circuitry while ensuring that the voltage reference, input amplifier, and reference ladder track well with variations of temperature and power supplies.
Internal Clock Operation (Tank) If the tank circuit is used, the resonant inductor should have a sufficiently high Q and a self-resonant frequency (SRF) of at least twice the intended oscillator frequency. Coilcraft's 1008HS-221, with an SRF of 700MHz and a Q of 45, works well for this application. Generate different clock frequency ranges by adjusting varactor and tank elements. An internal clock-driver buffer is included to provide sharp clock edges to the internal flash comparators. The buffer ensures that the comparators are simultaneously clocked, maximizing the ADCs' effective number of bits (ENOB) performance.
47k VCLK = 300mVp-p TO 1.25Vp-p 47pF 10k VTUNE 5pF 220nH TNKTNK+ CLK DRIVER VCLK 50 Z0 = 50 TNK+ 50 CLK DRIVER TNK0.1F 0.1F
47pF 47k
MAX1003
MAX1003
50 VTUNE = 0V TO 8V fOSC = 70MHz TO 110MHz VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287 (SOT23 PACKAGE) INDUCTOR COILCRAFT 1008HS-221.
Figure 6. Tank Resonator Oscillator
Figure 7. External Clock Drive Circuit
8
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Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
N
ANALOG INPUT tAD
N+1
N+2
50% TNK+ (INPUT CLOCK) tDCLK
1.4V DCLK tPD tSKEW
DATA OUT
1.4V
DATA VALID N - 1
DATA VALID N
Figure 8. MAX1003 Timing Diagram
OUTPUT CODE
External Clock Operation To accommodate designs that use an external clock, the MAX1003's internal oscillator can be overdriven by an external clock source as shown in Figure 7. The external clock source should be a sinusoid to minimize clock phase noise and jitter, which can degrade the ADCs' ENOB performance. AC couple the clock source (recommended voltage level is approximately 1Vp-p) to the oscillator inputs as shown in Figure 7.
111111 111110 111101
100001 100000 011111 011110 000011 000010 000001 000000 -FSR 2 0 1LSB INPUT VOLTAGE (_IN+ TO _IN-) FSR 2
Output Data Format
The conversion results are output on a dual, 6-bit-wide data bus. Data is latched into the ADC output latch following a pipeline delay of one clock cycle, as shown in Figure 8. Output data is clocked out of the respective ADC's data output pins (D_0 through D_5) on the rising edge of the clock output (DCLK), with a DCLK-to-data propagation delay (tPD) of 3.6ns. The MAX1003 outputs are +3.3V CMOS-logic compatible.
Transfer Function
Figure 9 shows the MAX1003's nominal transfer function. Output coding is offset binary with 1LSB = FSR / 63.
Figure 9. Ideal Transfer Function
_______________________________________________________________________________________ 9
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
__________Applications Information
The MAX1003 is designed with separate analog and digital power-supply and ground connections to isolate high-current digital noise spikes from the more sensitive analog circuitry. The high-current digital output ground (OGND) and analog ground (GND) should be at the same DC level, connected at only one location on the board. This will provide best noise immunity and improved conversion accuracy. Use of separate ground planes is strongly recommended. The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto the board, i.e., close to the connector. 10F electrolytic capacitors with low-ESR ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. The MAX1003 requires a +5V 5% power supply for the analog supply (VCC) and a +3.3V 300mV power supply connected to V CCO for the logic outputs. Bypass each of the VCC_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible (Table 2). Consult the evaluation kit manual for a suggested layout and bypassing scheme.
_____________Dynamic Performance
Signal-to-noise and distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 6-bit ADC can do no better than 38dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 20MHz sinusoid at a 90MHz clock rate. This FFT plot of the output shows the output level in various spectral bands. The plot has been averaged to reduce the quantization noise floor and reveal the low-amplitude spurs. This emphasizes the excellent spurious-free dynamic range of the MAX1003. The effective resolution (or effective number of bits) the ADC provides can be measured by transposing the equation that converts resolution to SINAD: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics).
Table 2. Bypassing
SUPPLY FUNCTION Analog Inputs Oscillator/Clock Converter Digital Q-Output Digital I-Output Buffer VCC/ VCCO 6 8 13 26 28 36 BYPASS TO GND/ OGND 7 11 12 27 27 19 CAPACITOR VALUE 0.01F 0.01F 0.01F 47pF 47pF 0.01F
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Low-Power, 90Msps, Dual 6-Bit ADC
__________________Pin Configuration
MAX1003
TOP VIEW
GAIN 1 IOCC+ 2 IOCC- 3 IIN+ 4 IIN- 5 VCC GND VCC TNK+ 6 7 8 9
36 VCC 35 DI5 34 DI4 33 DI3 32 DI2
MAX1003
31 DI1 30 DI0 29 DCLK 28 VCCO 27 OGND 26 VCCO 25 DQ0 24 DQ1 23 DQ2 22 DQ3 21 DQ4 20 DQ5 19 GND
TNK- 10 GND 11 GND 12 VCC 13 QIN- 14 QIN+ 15 QOCC- 16 QOCC+ 17 GND 18
SSOP
___________________Chip Information
TRANSISTOR COUNT: 6097
______________________________________________________________________________________
11
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003
________________________________________________________Package Information
SSOP2.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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